EDN

SystemVerilog reference verification methodology: Introduction

Verification is the single biggest challenge in the design of system-on-chip (SoC) devices and reusable IP blocks. Traditional verification methods struggle to keep pace with the ever-increasing size ...
EDN

How to improve FPGA-based ASIC prototyping with SystemVerilog

ASICs provide a solution for capturing high performance complex design concepts and preventing competitors from simply implementing comparable designs. However, creating an ASIC is a high-investment ...
Electronic Design

SystemVerilog: The Complete Solution

The electronics industry is constantly challenged by the ever-growing design and verification requirements for complex chips. With the IEEE-Std 1800-2005 System-Verilog standard, the industry has a ...
Electronic Design

Writing Testbenches Using SystemVerilog

Survey hardware design teams and you’ll find that the old saw is true: anywhere from 60% to 80% of the overall design cycle is consumed not with design itself, but rather with the nerve-wracking ...
Design-Reuse

SystemVerilog key to new design paradigm

SAN JOSE, Calif. — The SystemVerilog 3.1 specification is undergoing final reviews and Synopsys plans to have a synthesis tool for SystemVerilog assertions in the next 12 months, said Synopsys CEO ...
Electronics Weekly

Mentor and Synopsys give support to SystemVerilog design language

Mentor and Synopsys are putting their weight behind SystemVerilog, a nextgeneration hardware description language that extends Verilog to supportabstract behavioural design. What Cadence thinks of ...
Design-Reuse

SystemC Mixed-HDL IP Reuse Methodology

Due to increased complexity in today's embedded system designs, the importance of design reuse, verification, and debug becomes inescapable. Also, current mixed-language methodologies are not ...