A memory cache that shares the system bus with main memory and other subsystems. It is slower than inline caches and backside caches. See inline cache and backside cache. THIS DEFINITION IS FOR ...

A new technical paper titled “Risky Translations: Securing TLBs against Timing Side Channels” was posted by researchers at Ruhr University Bochum (Germany) and Cyber-Physical Systems of the German ...

A memory cache that resides next to the CPU, but shares the same system bus as other subsystems in the computer. It is faster than lookaside cache, but slower than a backside cache. See backside cache ...