EDN

Low-Power PCI Express PHYsical Layer

The PX1011B is a high-performance, low-power, single-lane PCI Express electrical PHYsical layer (PHY) that handles the low level PCI Express protocol and signaling. The PX1011B PCI Express PHY is ...
EDN

Structured ASIC devices embed PCI Express physical layer

Silicon-proven PCIe Subsystem Offers High Performance, Low Risk Alternative to Traditional ASIC, FPGA Options Santa Clara, Calif.—ChipX, the Structured ASIC leader, today announced the CX6100 family ...
Nasdaq

Teledyne LeCroy Announces Industry-First Capability to Analyze PCI Express® Across Physical and Protocol Layers

CHESTNUT RIDGE, N.Y., Feb. 23, 2021 /PRNewswire/ -- Teledyne LeCroy introduced the CrossSync™ PHY interposers and software options, enabling the first-ever link between an oscilloscope and a protocol ...
Design-Reuse

Virage Logic Introduces Volume Production-Proven SiPro PCI Express PHY IP

SAN FRANCISCO-- July 28, 2009 --Virage Logic Corporation (NASDAQ:VIRL), the semiconductor industry's trusted IP partner, today announced its new offering, a silicon and volume production-proven ...
Design-Reuse

Rambus Unveils Turbo PCI EXPRESS* PHY Platform

LOS ALTOS, Calif., June 21, 2004 - Rambus Inc. (Nasdaq: RMBS), a leading developer of chip interface products and services, today unveiled its Turbo PCI Express* physical layer (PHY) platform which ...
Electronic Design

Testing Races Ahead to Handle High-Speed Connectivity

Connectivity is becoming a bottleneck in the age of AI. To unclog the interconnects between processors, accelerators, and memory, high-speed serial interfaces based on the PCIe Gen 6 bus are in the ...
Electronic Design

Understanding Gained One Layer at a Time

PCI Express (PCIe) is a typical protocol that consists of several distinct layers: physical with logical sub-block, data link, and transaction. Each of the layers actually is a separate protocol ...
Business Wire

PLDA and M31 Announce a Compliant PCI Express® 3.0 Solution Including PLDA’s XpressRICH3 Controller and M31’s PHY IP for the TSMC 28HPC+ Process Node at 8 GT/s

SAN JOSE, Calif.--(BUSINESS WIRE)--PLDA, the industry leader in PCI Express® and interface IP solutions and M31, a global silicon intellectual property (IP) boutique, today announced that their ...
아시아경제

[Featured Stock] Qualitas Semiconductor Develops World-Class Technology for the First Time... Anticipated to Lead the CXL Market

Qualitas Semiconductor, a specialist company in the development of ultra-high-speed interface IP (intellectual property), is showing strong performance. The news that it has developed the PCIe ...
Nasdaq

Teledyne LeCroy Enables First-Ever Full Picture of PCIe with Launch of CrossSync™ PHY

CHESTNUT RIDGE, N.Y.--(BUSINESS WIRE)-- Teledyne LeCroy, a business unit of Teledyne Technologies Incorporated (NYSE: TDY), introduced the CrossSync™ PHY interposers and software options, enabling the ...
Semiconductor Engineering

How The Doubling Of Interconnect Bandwidth With PCI Express 6.0 Impacts IP Electrical Validation

As a result of the innovations taking place in CPUs, GPUs, accelerators, and switches, the interface in hyperscale datacenters now requires faster data transfers both between compute and memory and ...