Implementation of a modular cache data structure, to simulate the working of multiple cache level hierarchy design with victim cache for multiple configurations (cache size, block size and ...
A technical paper titled “Improving the Representativeness of Simulation Intervals for the Cache Memory System” was published by researchers at Complutense University of Madrid, imec, and KU Leuven.
• Designed a generic Cache simulator module and modeled L1, L2 caches augmented with a Victim Cache. • Implemented using C++ and evaluated with SPEC address traces for gcc, perl, vortex, compress and ...
Results that may be inaccessible to you are currently showing.
Hide inaccessible results
Feedback