GitHub

Fully Automatic Washing Machine Controller (Verilog HDL)

This repository contains the complete design, Verilog HDL code, simulation testbenches, and documentation for a Fully Automatic Washing Machine Controller project. The goal is to model and simulate ...
GitHub

A multi-cycle processor of a cpu designed according to the instruction set (assembly language) of RISC-V using System Verilog HDL.

This project implements a multicycle RISC-V processor using SystemVerilog. It is designed to execute a subset of the RISC-V instruction set architecture (ISA) and demonstrates a step-by-step ...
IEEE

Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning

Abstract: Recent advancements in large language models (LLMs) have sparked significant interest in the automatic generation of Register Transfer Level (RTL) designs, particularly using Verilog.
IEEE

Exploring Large Language Models for Verilog Hardware Design Generation

Abstract: Deep Learning Large Language Models (LLMs) have the potential to automate and simplify code writing tasks. One of the emerging applications of LLMs is hardware design, where natural language ...