GitHub

ECE 4750 Section 2: RTL Design with Verilog

This repository contains the code and documentation for ECE 4750 Section 2 on the RTL design with Verilog. You can find the actual section document in the repo here: ...
IEEE

Exploring Large Language Models for Verilog Hardware Design Generation

Abstract: Deep Learning Large Language Models (LLMs) have the potential to automate and simplify code writing tasks. One of the emerging applications of LLMs is hardware design, where natural language ...
IEEE

Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning

Abstract: Recent advancements in large language models (LLMs) have sparked significant interest in the automatic generation of Register Transfer Level (RTL) designs, particularly using Verilog.
GitHub

Aashi881/ARM_AMBA_Design

A comprehensive Verilog implementation of ARM AMBA (Advanced Microcontroller Bus Architecture) protocols including AHB, APB, and AXI standards. This project is a complete redesign and enhancement ...