IEEE

High Resistance and Low Variation 8Kb SOT-MRAM Compute-in-Memory Array Based on 1T-1R Cell Structure

Abstract: Nonvolatile memories (NVMs) have emerged as promising candidates for efficient analog compute-in-memory (CIM). However, high power consumption and large variations in NVMs are key factors ...
IEEE

A Scalable External Memory Access and On-Chip Storage Architecture for Edge-AI Accelerators : – Multi-Path Rolling Data Refresh and Layer-Wise Bank Allocation

Abstract: For resource-constrained AI accelerators applied in edge computing, achieving high power efficiency in neural network (NN) model computation is crucial. However, current designs often ...