GitHub

Espresso Logic Minimizer - Modernized Edition

This repository contains a maintained and modernized version of the Espresso logic minimizer, originally developed at the University of California, Berkeley. Espresso is a heuristic multi-valued PLA ...
IEEE

Varactor-Integrated Single-Port Antenna Array With Element-Wise Coupling Optimization for Scalable Beamforming in 6G Massive MIMO Systems

Abstract: This paper presents a high-efficiency reconfigurable antenna array architecture that utilizes varactor diodes for beam steering at 28 GHz. To enable efficient beamforming without increasing ...
Opinion

The 3D-Flow Architecture Breakthrough: A Universal, Scalable Digital Processor for Real-Time Pattern Recognition in High-Rate Data Streams -- A Platform to Save Millions of ...

Public records clearly shows that for the past 25 years, CERN has repeatedly built inadequate FPGA-based Level-1 Triggers, necessitating multiple rebuilds. During the Higgs boson discovery ...
IEEE

Evaluation of an Optically Programmable Digital Impedance Surface (DIS) for Antenna and Reflect Array Applications

Abstract: This paper presents the design and experimental validation of an optically programmable Digital Impedance Surface (DIS). Utilizing discrete binary impedance switching, a novel triangular ...
GitHub

accelerated-logic-simulator

this is the results of 2 years of development of the first logic simulator that is based on HW instead of SW. Project by Max Nigri ...