GitHub

ECE 4750 Section 2: RTL Design with Verilog

This repository contains the code and documentation for ECE 4750 Section 2 on the RTL design with Verilog. You can find the actual section document in the repo here: ...
IEEE

Exploring Large Language Models for Verilog Hardware Design Generation

Abstract: Deep Learning Large Language Models (LLMs) have the potential to automate and simplify code writing tasks. One of the emerging applications of LLMs is hardware design, where natural language ...
IEEE

IEEE Communications Surveys and Tutorials

Abstract: I welcome you to the fourth issue of the IEEE Communications Surveys and Tutorials in 2021. This issue includes 23 papers covering different aspects of communication networks. In particular, ...